fn6987 rev 0.00 page 1 of 10 october 26, 2009 fn6987 rev 0.00 october 26, 2009 qlx111grx 11.1gb/s lane extender datasheet the qlx111grx is a settable single-channel receive- side equalizer with extended functionality for advanced protocols operating with line rates up to 11.1gb/s such as 10g ethernet (10gbase-cr). the qlx111grx compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to at least 10m on 28awg cable. the small form factor, highly-integrated design is ideal for high-density data transmission applications including active copper cable assemblies. the equalizing filter within th e qlx111grx can be set to provide optimal signal fide lity for a given media and length. the compensation level for the filter is set by two external control pins. operating on a single 1.2v power supply, the qlx111grx enables per channel throughputs of 10gb/s to 11.1gb/s while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125, and 2.5gb/s. the qlx111grx uses current mode logic (cml) input/output and is packaged in a 3mmx3mm 16 lead qfn. los support is included for module applications. features ? supports data rates up to 11.1gb/s ? low power (<135mw) ? low latency (<500ps) ? single channel equalizer in a 3mmx3mm qfn package for straight route-through architecture and simplified routing ? adjustable equalizer boost ? supports 64b/66b encoded data ? long run lengths ? line silence preservation ?1.2v supply voltage ?los support applications ? sfp+ active copper cable modules ? qsfp active copper cable modules ? 10g ethernet (10gbase-cr) ?xfi ? 40g ethernet (40gbase-cr4) ? fibre channel ? high-speed active cable assemblies ? high-speed printed circuit board (pcb) traces benefits ? thinner gauge cable ? extends cable reach greater than 3x ?improved ber typical application circuit
qlx111grx fn6987 rev 0.00 page 2 of 10 october 26, 2009 pin configuration qlx111grx (16 ld qfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # QLX111RIQT7 ql111 0 to +70 16 ld qfn 7? prod. tape & reel; qty 1,000 l16.3x3b qlx111riqsr ql111 0 to +70 16 ld qfn 7? sample reel; qty 100 l16.3x3b note: these intersil pb-free plastic packag ed products employ specia l pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are ms l classified at pb-fre e peak reflow temper atures that meet o r exceed the pb-free requirements of ipc/jedec j std-020. 1 3 4 15 v dd in[p] in[n] v dd gnd dt los gnd 16 14 13 2 12 10 9 11 6 578 v dd out[p] out[n] v dd gnd cp[a] cp[b] gnd pin descriptions pin name pin number description v dd 1, 4, 12, 9 power supply. 1.2v supply voltage. the us e of parallel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pins for broad high-frequen cy noise suppression. in[p,n] 2, 3 equalizer 1 differential input, cml. the us e of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. cp[a,b] 6, 7 control pins for setting th e equalizer. cmos logic inputs. pins are read as a 2-digit number to set the boost level. pins are internally pulled up and down through a 23k ? resistor. out[p,n] 11, 10 equalizer differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. los 14 los indicator. high output when equalized in signal is below dt threshold. open drain output internally pulled up to v dd with a 10k ? resistor. dt 15 detection threshold. re ference dc voltage threshold for input signal power detect ion. data output out is muted when the power of the equalized versio n of in falls below the th reshold. tie to ground to disable electrical idle preservation and always enable the limiting amplifier. gnd 5, 8, 13, 16 ground
qlx111grx fn6987 rev 0.00 page 3 of 10 october 26, 2009 absolute maximum ratings thermal information supply voltage (v dd to gnd) . . . . . . . . . . . . -0.3v to 1.3v voltage at all input pins . . . . . . . . . . . -0.3v to v dd + 0.3v esd rating high speed pins . . . . . . . . . . . . . . . . . . . . . 1.5kv (hbm) all other pins . . . . . . . . . . . . . . . . . . . . . . . . 2kv (hbm) operating ambient temperature range . . . . . . 0c to +85c storage ambient temperature range . . . . -55c to +150c maximum junction temperature . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. operating conditions parameter symbol condition min typ max units supply voltage v dd 1.1 1.2 1.3 v operating ambient temperature t a 02570c bit rate nrz data applied to any channel 2.5 11.1 gb/s control pin characteristics typical values are at v dd = 1.2v, t a = +25c, and v in = 600mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +85c. parameter symbol condition min typ max units input low logic level v il di, clk, enb 0 0 350 mv input high logic level v ih di, clk, enb 750 v dd mv output low logic level v ol los, do 0 0 250 mv output high logic level v oh los, do 1000 v dd mv input current current draw on digital pi n, i.e., cp[a,b], di, clk, enb 30 100 a electrical specifications typical values are at v dd = 1.2v, t a = +25c, and v in = 600mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +85c. parameter symbol condition min typ max units notes supply current i dd 111 ma cable input amplitude range v in measured differentially at data source before encountering channel loss 600 1200 1600 mv p-p 1 dc differential input resistance measured on input channel in 80 100 120 ? dc single-ended input resistance measured on input channel in[p] or in[n] 40 50 60 ? input return loss (differential) s dd 11 100mhz to 7.5ghz 12 db 2 input return loss (common mode) s cc 11 100mhz to 7.5ghz 7 db 2 input return loss (com. to diff. conversion) s dc 11 100mhz to 7.5ghz 35 db 2 output amplitude range v out measured differentially at out[p] and out[n] with 50 ? load on both output pins 500 650 800 mv p-p differential output impedance measured on out 80 100 120 ? output return loss (differential) s dd 22 100mhz to 7.5ghz 10 db 2 output return loss (common mode) s cc 22 100mhz to 7.5ghz 5 db 2
qlx111grx fn6987 rev 0.00 page 4 of 10 october 26, 2009 output return loss (com. to diff. conversion) s dc 22 100mhz to 7.5ghz 32 db 2 output residual deterministic jitter dj 10gb/s; up to 10m 28awg standard twin-axial cable (approx. -27db @ 5ghz); 1200mv p-p ?? v in ? 1600mv p-p 0.15 ui 1, 3, 4 output residual deterministic jitter rj 10gb/s; up to 10m 28awg standard twin-axial cable (approx. -27db @ 5ghz); 1200mv p-p ?? v in ?? 1600mv p-p 1.3 ps rms 1, 3, 4 output transition time t r , t f 20% to 80% 35 ps 5 propagation delay from in to out 500 ps los assert time time to assert loss-of-signal (los) indicator when transitioning from active data mode to line silence mode 50 s 6 los de-assert time time to de-assert loss-of-signal (los) indicator when transitioning from line silence mode to active data mode 50 s 6 data-to-line silence response time time to transition from active data to line silence (muted output) on 10m 28awg standard twin-axial cable at 10gb/s 50 s 6 line silence-to-data response time time to transition from line silence mode (muted output) to active data on 10m 28awg standard twin-a xial cable at 10gb/s 50 s 6 notes: 1. after channel loss, differential amplitudes at qlx111grx inpu t must meet the input voltage range specified in ?absolute maximum ratings? on page 3. 2. temperature = +25c, v dd = 1.2v. 3. output residual jitter is the difference between the total jitt er at the lane extender output and the total jitter of the tra nsmitted signal (as measured at the input to the channel). total jitter (t j ) is dj pp + 14.1 x rj rms . 4. measured using a prbs 2 7 -1 pattern. deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. 5. rise and fall times measured using a 1ghz clock with a 20ps edge rate. 6. for active data mode, cable input amplitude is 300mv p-p (differential) or greater. for line silence mode, cable input amplitude is 20mv p-p (differential) or less. electrical specifications typical values are at v dd = 1.2v, t a = +25c, and v in = 600mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +85c. (continued) parameter symbol condition min typ max units notes
qlx111grx fn6987 rev 0.00 page 5 of 10 october 26, 2009 typical performance characteristics performance is measured using the test setup illustrated in fi gure 1. the signal from the pattern generator is launched into the twin-ax cable using an sma adapter card. the chip evaluation board is connected to the output of the cable through another adapter card. th e qlx111grx output signal is then visualized on a scope to determine signal integrity parameters such as jitter (note 7). figure 1. device characterization set up figure 2. jitter vs cable length at 10gb/s (boost levels 0-3) figure 3. qlx111grx 10gb/s output for a 10m 28awg cable note: 7. prior to the tapeout, the data in figure s 2 and 3 represents simulation s approximating the conditions of setup in figure 1, n ot measured data. pattern generator sma adapter card 100o twin-axial cable sma adapter card qlx111g eval board oscilloscope ?
qlx111grx fn6987 rev 0.00 page 6 of 10 october 26, 2009 operation the qlx111grx is an advanced lane-extender for high-speed interconnects. a functional diagram of qlx111grx is shown in figure 4. in addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the qlx111grx contains unique integrated features to preserve special signaling protocols typically broken by other equalizers. the signal detect function is used to mute the channel output when the equalized signal falls below the level determined by the detection threshold (dt) pin voltage. this function is intended to preserve periods of line silence (?quiescent state? in infiniband contexts). furthermore, the output of the signal detect/dt comparator is used as a loss of signal (los) indicator to indicate the absence of a received signal. as illustrated in figure 4, the core of the high-speed signal path in the qlx111grx is a sophisticated equalizer followed by a limiting amplifier. the equalizer compensates for skin loss, dielectric loss, and impedance discontinuities in the transmission channel. the equalizer is followed by a limiting amplification stage that provides a clean output signal with full amplitude swing and fast rise-fall times for reliable signal decoding in a subsequent receiver. adjustable equalization boost qlx111grx features a settable equalizer for custom signal restoration. the flexibility of this adjustable compensation architecture enables signal fidelity to be optimized on a channel-by-channel basis, providing support for a wide variety of channel characteristics and data rates ranging from 2.5gb/s to 11.3gb/s. because the boost level is externally set rather than internally adapted, the qlx111grx provides reliable communication from the very first bit transmitted. there is no time needed for adaptation and control loop convergence. furthermore, there are no pathological data patterns that will cause the qlx111grx to move to an incorrect boost level. control pin boost setting the connectivity of the cp pins are used to determine the boost level of qlx111grx. table 1 defines the mapping from the 2-bit cp word to the 5 available boost levels. cml input and output buffers the input and output buffers for the high-speed data channel in the qlx111grx ar e implemented using cml. equivalent input and output circuits are shown in figures 6 and 7. figure 4. functional diagram of a single channel within the qlx111grx table 1. mapping between boost level and cp- pin connectivity cp[a] cp[b] boost level no connect no connect 0 no connect gnd 1 no connect vdd 2 gnd no connect 3 gnd gnd 4 figure 5. gain profile for various boost settings in qlx111grx
qlx111grx fn6987 rev 0.00 page 7 of 10 october 26, 2009 line silence/quiescent mode line silence is commonly broken by the limiting amplification in other equalizers. this disruption can be detrimental in many systems that rely on line silence as part of the protocol. the qlx111grx contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity-enhancing benefits of limiting amplification during active data transmission. line silence is detected by measuring the amplitude of the equalized signal and comparing that to a threshold set by the voltage at the dt pin. when the amplitude falls below the threshold, the output driver stage is muted. los indicator pin los is used to output the state of the muting circuitry to serve as a loss of signal indicator for the device. this signal is directly derived from the muting signal off the dt-threshold signal detector output. the los signal goes high when the power signal is below the dt threshold and low when the power goes above the dt threshold. this feature is meant to be used in optical systems (e.g. sfp+) where there are no quiescent or electrical-idle states. in these cases, the dt threshold is used to determine the sensitivity of the los indicator. detection threshold (dt) pin functionality the qlx111grx is capable of maintaining periods of line silence by monitoring each channel for loss of signal (los) conditions and subsequently muting the outputs of a respective channel when such a condition is detected. a reference voltage applied to the detection threshold (dt) pin is used to set the los threshold of the internal signal detection circuitry. voltage control on the dt pin is done via two external resistors. both a pull-up and pull-down resistor are tied to the dt pin, with suggested values indicated in figure 8. other values of the resistors may also be applicable; therefore customers are advised to verify dt settings for their specific application. figure 6. cml input equivalent circuit for the qlx111grx figure 7. cml output equivalent circuit for the qlx111grx
qlx111grx fn6987 rev 0.00 page 8 of 10 october 26, 2009 typical application reference design figure 8. typical application reference design figure 9. typical qlx111grx application schematic 16 15 14 13 5 6 7 8 12 11 10 9 1 2 3 4 in[p] v dd in[n] v dd 1.2v 1.2v out[p] out[n] v dd v dd gnd cpa cpb gnd 1.2v 1.2v gnd gnd 1.2v dt 2.5/3.3v qlx111grx lane extender los 69 50 10k see table 6. for setting cp see table 1 for setting cp boost level
fn6987 rev 0.00 page 9 of 10 october 26, 2009 qlx111grx intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about q:active ? intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. to address this, intersil has developed its groundbreaking q:active? product line. by integrating its analog ics inside cabling interconnects, intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow?s datacenters. this new technology transforms passive cabling into intelligent ?roadways? that yield lower operating expenses and capital expenditures for the expanding datacenter. intersil lane extenders allow greater reach over existing cabling while reducing the need for thicker cables. this significantly reduces cable weight and clutter, increases airflow, and improves power consumption.
qlx111grx fn6987 rev 0.00 page 10 of 10 october 26, 2009 package outline drawing l16.3x3b 16 lead quad flat no-lead plastic package rev 1, 4/07 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recomme nded land pattern top view bottom view side view 9 ( 2. 80 typ ) ( 1. 70 ) (4x) 0.15 ( 12x 0 . 5 ) ( 16x 0 . 60) ( 16x 0 . 23 ) 0 . 90 0.1 index area pin 1 6 a 3.00 b 3.00 12 4 4 5 8 16x 0.40 0.10 5 0 . 2 ref c 0 . 00 min. 0 . 05 max. b c ma 0.10 c - 0.05 base plane 0.10 c see detail "x" c 0.08 seating plane + 0.07 16x 0.23 16 13 12x 1.5 4x 0.50 1 6 pin #1 index area 1 .70 + 0.10 - 0.15
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